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XMOS Processor - XS1-L1-64

2 €2.00

Availability: Retired

The XS1 family of devices features a multi-threaded processor architecture constructed from XCore processors connected by communication links. The architecture is scalable and any number of XCore processors can be connected together. 

Applications are developed using a combination of XC, C, and C++. XC provides extensions to C that simplify the control over concurrency, I/O and time. These extensions map directly to XS1 device resources making it easy to write embedded applications that require a blend of control code, DSP, and interfacing.

Features:

  • Event driven processing at 400MIPS
  • 64 kBytes of SRAM
  • 8 threads
  • 36 user I/O pins
  • 8 kBytes of OTP memory for application boot code and security keys
  • A typical power consumption of 450µW/MHz

Documents:

Community:

Description

The XS1 family of devices features a multi-threaded processor architecture constructed from XCore processors connected by communication links. The architecture is scalable and any number of XCore processors can be connected together. 

Applications are developed using a combination of XC, C, and C++. XC provides extensions to C that simplify the control over concurrency, I/O and time. These extensions map directly to XS1 device resources making it easy to write embedded applications that require a blend of control code, DSP, and interfacing.

Features:

  • Event driven processing at 400MIPS
  • 64 kBytes of SRAM
  • 8 threads
  • 36 user I/O pins
  • 8 kBytes of OTP memory for application boot code and security keys
  • A typical power consumption of 450µW/MHz

Documents:

Community:

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