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Bus Blaster v3

34.95 €34.95

Availability: Retired

Bus Blaster v3 is an experimental, high-speed JTAG debugger from Dangerous Prototypes.Thanks to a reprogrammable buffer, a simple update over USB makes Bus Blaster compatiblewith many different JTAG debugger types in the most popular open source software.Based on FT2232H with high-speed USB 2.0Buffered interface works with 3.3volt to 1.8volt targetsReprogrammable buffer is compatible with multiple debugger typesCompatible with 'jtagkey', 'KT-link' programmer settings in OpenOCD,urJTAG, and moreships with JTAGkey compatible buffer image pre-programmedShould support Serial Wire Debug when availableMini-CPLD development board: self programmable, extra CPLD pins to headerOpen source (CC-BY-SA)Updates in v3:Fitted in a DP8049 (80x49 mm) standard PCB, case available hereAdded series resistors to input and output pins to protect against damage and noiseSwapped FT2232 clock output to CPLD pin with global clock feature for potential logic analyzer modeEach unit is tested before it ships.Bus Blaster Manual Bus Blaster design overview Bus Blaster forum CPLD buffer logic overview This open source hardware and software is distributed in the hope that it will be useful, butWITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. If you encounter any problems when using this product, please request technical support in the forum.

Description

Bus Blaster v3 is an experimental, high-speed JTAG debugger from Dangerous Prototypes.Thanks to a reprogrammable buffer, a simple update over USB makes Bus Blaster compatiblewith many different JTAG debugger types in the most popular open source software.Based on FT2232H with high-speed USB 2.0Buffered interface works with 3.3volt to 1.8volt targetsReprogrammable buffer is compatible with multiple debugger typesCompatible with 'jtagkey', 'KT-link' programmer settings in OpenOCD,urJTAG, and moreships with JTAGkey compatible buffer image pre-programmedShould support Serial Wire Debug when availableMini-CPLD development board: self programmable, extra CPLD pins to headerOpen source (CC-BY-SA)Updates in v3:Fitted in a DP8049 (80x49 mm) standard PCB, case available hereAdded series resistors to input and output pins to protect against damage and noiseSwapped FT2232 clock output to CPLD pin with global clock feature for potential logic analyzer modeEach unit is tested before it ships.Bus Blaster Manual Bus Blaster design overview Bus Blaster forum CPLD buffer logic overview This open source hardware and software is distributed in the hope that it will be useful, butWITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. If you encounter any problems when using this product, please request technical support in the forum.

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